Fast VLSI Implementation for Low Power Motion Estimation Removing Redundant Memory Data Access

| This paper presents a new VLSI architecture of the Motion Estimation in MPEG-2. Previously , a number of full search block matching algorithms (BMA) and architectures using systolic array have been proposed for motion estimation. However, the architectures have an ineeciently large number of external memory access. Recently, to reduce the number of accesses in one candidate block, a block matching method within a search area to reuse the search data is provided using systolic process arrays. To further reduce the data access and computation time during the block matching, we propose a new approach through the reuse of the previously-search data in two dimensions. Our new architecture in this paper is an extension from our previous work such that we reuse the previously searches area not only between two consecutive columns but also between two consecutive rows, so as to entirely remove redundant memory access. Experimental results show the eeciency of our algorithm.